1. Field of the Invention
The present invention relates to a semiconductor device in which a plurality of vertical type construction transistors such as heterojunction bipolar transistors (HBTs) are included in one and the same substrate.
2. Description of the Related Art
Progress has been made in the epitaxial growth technique for making a semiconductor layer of Group III-V compounds, so that a heterojunction can be formed with high accuracy. Due to the progress in such a technique, a vertical type construction transistor with a heterojunction such as a heterojunction bipolar transistor (HBT) or a hot electron transistor has been actively and widely studied. In addition, an integrated circuit including such vertical type construction transistors has been actively and widely studied.
In general, in a semiconductor device in which a plurality of transistors are included in one and the same substrate, it is necessary to connect the transistors to each other. In FIG. 6, a vertical type construction transistor 4 includes an emitter electrode 1, a base electrode 2 and a collector electrode 3. In order to connect the vertical type construction transistor 4 to other transistors adjacent thereto (not shown), an emitter interconnection 11, a base interconnection 12, and a collector interconnection 13 are provided for the electrodes 1, 2, and 3, respectively, as is shown in FIG. 6. Depending on the arrangement of the adjacent transistors, two of the three interconnections 11, 12, and 13 are required to intersect with each other. In this specification, intersection of two interconnections means that two interconnections formed on the same support cross with each other. FIG. 6 shows an exemplary structure in which the emitter interconnection 11 intersects with the collector interconnection 13 in an intersecting portion P. FIG. 7A is an enlarged plan view of the intersecting portion P shown in FIG. 6. FIG. 7B is a cross-sectional view of the intersecting portion P. In order to prevent the emitter interconnection 11 and the collector interconnection 13 both formed on a substrate 25 from being electrically in contact with each other, in the intersecting portion P, the collector interconnection 13 overlaps the emitter interconnection 11 with an insulating film 20 interposed there-between.
With the above structure, a parasitic capacitance is generated in the intersecting portion P due to the insulating film 20 formed between the two interconnections 11 and 13. There arises a problem in that the parasitic capacitance degrades the transistor characteristics. However, if the electrode area of the intersecting portion P is minimized in order to reduce the parasitic capacitance as a countermeasure against the above problem, this disadvantageously produces a parasitic resistance. The parasitic resistance also degrades the transistor characteristics. Especially in a vertical type construction transistor which operates at a high speed and a high frequency, it is a critical problem to reduce the parasitic capacitance and the parasitic resistance for enhancing the device characteristics.
Another conventional structure for reducing the parasitic capacitance in the intersecting portion P is shown in FIGS. 8A and 8B. In the shown conventional structure, a collector interconnection 13 spatially overlaps an emitter interconnection 11 so as to intersect with no insulating film interposed therebetween. This conventional structure which is referred to as an air-bridge structure is suitable for reducing the parasitic capacitance.
As is shown in FIG. 8B, part of the collector interconnection 13 is spatially separated from a substrate 25 with a space 21. That is, the part of the collector interconnection 13 is not held by the substrate 25. It is preferable to make the space 21 as small as possible so that the collector interconnection 13 can have an appropriate strength. Accordingly, the emitter interconnection 11 is preferably formed to be narrow and thin. However, such a narrow and thin emitter interconnection 11 may increase the parasitic resistance. Moreover, in the air-bridge structure, the interconnections are likely to be short-circuited because of a small load from the surface of the substrate. In addition, the production process for the air-bridge structure is complicated. Therefore, the production cost is increased, and the reliability of the device is decreased.
In a semiconductor device including a plurality of transistors in one and the same substrate, the heat generation during the operation also causes a problem. A GaAs semiconductor has a larger band-gap than that of an Si semiconductor by about 0.3 eV, so that a vertical type construction transistor which uses the GaAs semiconductor should operate at a higher voltage. Thus, the power consumption increases. The increase in power consumption leads to an increase in heat generation. The heat conductivity of the GaAs semiconductor is 0.46 W/.degree. cm C. which is about 1/3 as compared with that of the Si semiconductor. Accordingly, it is important for the vertical type construction transistor to efficiently dissipate the heat generated by the device operation. In a conventional vertical type construction transistor, a device called a plated heat sink (PHS) is used. In this method, a semiconductor substrate is ground to have a thickness of about 20 .mu.m, and a metal with good heat conductivity such as gold is formed on a rear face of the substrate. As a result, the heat is dissipated from the rear face of the semiconductor substrate.
This method includes production process steps for the rear face of the substrate, so that the entire production process is complicated. Especially, the registration for the front face and the rear face of the substrate is complicated and difficult. Moreover, the substrate is made thinner, so that the possibility that the substrate is damaged is increased. Thus, the production cost is increased. Also the formation of gold on the rear face of the substrate causes such problems as the residual stress and the increase in production cost.